Memory tests on random access memory (RAM) integrated circuits, such as DRAMs and SRAMs and the like are typically performed by the manufacturer during production and fabrication and also by a downstream manufacturer of a computer or processor controlled system as well as by an end-user during computer initialization to determine if the circuits are operating as intended. The testing is typically performed by a memory controller or processor (or a designated processor in a multi processor machine) which runs a testing program.
Random access memories are usually subjected to data retention tests and/or data march tests. In data retention tests, every cell of the memory is written and checked after a pre-specified interval to determine if leakage current has occurred that has affected the stored logic state. In a march test, a sequence of read and/or write operations is applied to each cell, either in increasing or decreasing address order. Such testing ensures that hidden defects will not be first discovered during operational use, thereby rendering end-products unreliable. In order to reduce the number of address lines and time required to conduct a memory test, the memory test may be done in a so-called compressed mode in which banks of memory locations are tested in parallel, with the memory locations of one bank being tested against those of another, rather than one at a time.
An example of a conventional compressed memory test circuit is shown in FIG. 1. A random access memory device includes multiple bank memory arrays 10. Each array includes storage cells organized in rows and columns for storing data. Each storage cell is addressable, i.e. responsive to address select signals. Address specification is made by a row decoder and a column decoder (not shown), which are commonly shared by memory arrays.
When placed in a memory test mode, a predetermined test data pattern consisting of high binary logic voltage levels (high logic levels) and/or low binary logic voltage levels (low logic levels) is written concurrently into each cell of the bank of memory arrays 10. The test data stored in each cell is subsequently read from each cell and compared to data read from a parallel bank memory array cell by comparators 12 to determine if the compared data is in a mutually identical logic state. A properly functioning memory will have stored the identical logic state in each cell. The comparators 12 will output a signal based upon the coincidence or non coincidence of the compared data. The compared data is outputted on data lines 16 by MUX 14. Data lines 16 are connected to error detection circuits 18. Should the data from each compared cell not be coincident, indicating a defective memory cell, error detection circuit 18 will output a signal on one of a plurality of error detection lines 22, 27. The error detection lines 22, 27 are connected to tri-state data control lines 24 via logic circuitry 26. The tri-state data control lines are connected to outputs DQ0-DQ3. The outputs DQ0-DQ3 are connected to a controller or processor 20.
The signal output from outputs DQ0-DQ3 can be in one of three states: a HIGH logic level indicating a high binary logic voltage level, a LOW logic level indicating a low binary logic level, or a high impedance level, also known as a tri-state signal, in which case the lines do not cause any loading or sinking of the associated circuitry. If the compared data is coincident, indicating proper memory cell functioning, a signal as determined by the error indicating circuit 18 will be sent to the logic circuitry 26 via the error indicating lines 22, 27. The logic circuitry 26 will output a signal via tri-state data control lines 24 to outputs DQ0-DQ3. Outputs DQ0-DQ3 will conduct either a HIGH logic level or a LOW logic level to a controller 20, which will be interpreted by the controller 20 as a proper memory function signal. Should the compared data be non coincident, indicating a memory cell failure, a different signal than that indicating coincidence of data will be sent to the logic circuitry 26 from the error indicating circuit 18 via the error indicating lines 22, 27. The logic circuitry will output a signal representing a memory failure to outputs DQ0-DQ3 via tri-state data control lines 24. Outputs DQ0-DQ3 will conduct a tri-state signal to controller 20. The controller will interpret this signal as a memory operation failure.
The circuitry necessary for performing a memory test is required to be built onto the memory device. Lines dedicated solely for the error detection signals are typically provided, occupying space on the memory device. Although the read compression technique can be used to some extent to reduce the number of addressing lines needed for the memory test, memory devices of increasingly larger storage capacities or higher bandwidths have been developed which of necessity increases the number of data lines required for addressing and for providing the error test results to the processor or controller. As the memory devices include increasingly greater number of memory cells, there is a corresponding increase in the size of the memory device necessary to accommodate the additional circuitry and associated test lines. Thus, the problem exists of how to maintain the memory test function while utilizing decreased space within the device for the necessary associated testing circuitry.
The present invention has been designed to overcome some of the limitations associated with memory testing functions.